Performance of the CMP16C chip
(Pass1 data from ASIC Chip Test Stand at Fermilab)


  • Introduction.

  • Data from Pass1.

  • Summary of results from Pass1.

  • Data from the test stand for the chips CMP16B and CMP16C installed on the joint boards AD96D #6,7,8,9 and 10



  • Introduction.

    • The ASIC chips CMP16C (Mar. 1999 submission, total 30 chips) have been tested on the ASIC chip test stand at Fermilab in June, 1999.
    The first pass thru the chips (Pass1) included measurements of thresholds and noise at JTAG(threshold)=110,130 and 150 with input capacitance Cin=180 pF and zero delay. From these data the gains and discriminator offsets were found as well.
    From total 30 chips 4 chips (79, 81, 90 and 97) were found dead, in two chips (100 and 101) no signal was found at JTAG=150. Therefore only 24 chips are presented in the results. The dead channels were found in the chips 82 (##5,9), 83 (#16), 103 (##3,5,7) and 104 (#5). Also chips 82,83 and 102 have oscillations at JTAG=150 in almost all channels.

    The time measurements were done at Cin=180 pF as well and mostly at JTAG=150. Because the measured time is the time difference between signals from chip and pulser the observed slewing time of the chip has two contributions - from the chip and from the pulser and they can partly compensate each other yielding biased (underestimated) chip slewing time. This was the case for all previous measurements untill N.Bondar fixed the problem by reducing pulser slewing time up to 0.5 nsec. Meanwhile the software method was developed to separate these two contributions as well. It takes advantage of two time measurements made for each chip with one and the same amplitude of pulser signal for the TDC start but different amplitude of input signal for the chip (output signal from the chip served as TDC stop). Two sets of data were taken for each CMP16C chip, one with 1:10 attenuation of input test pulse, another - with 1:2 attenuation. The code fits two data sets with a sum of two second order polynomials each describing chip and pulser slewing time contributions, see example for chip #75. The unbiased maximum slewing time for the chip defined from corresponding fitted function as the max. time difference between two signals in the interval of Qin=40-800 fC turned out to be 2.8 nsec, while the maximum slewing time for the pulser - 0.5 nsec (DAC=500-4000). Total 26 chips were measured (75 76 77 78 80 82 83 84 85 86 87 88 89 91 92 93 94 95 96 98 99 100 101 102 103 104), chip 83 had bad time distributions in all channels (excluded from summary), chip 103 had funny distributions in ch. 6 and 15.

    After the pass the chips CMP16C (and CMP16B) have been installed on the joint boards AD96D and tested again on the ASIC chip test stand. The results of these tests (thresholds, noise and slewing time) are presented here as well.

  • Data from Pass1.

    • Threshold, noise, gain and discriminator offset are in Fig.1(see also the table below):
    PageHistograms
    1 Threshold and noise distributions in fC (per channel) , JTAG=150
    2-3 Thresholds per channel (fC), chip by chip, JTAG=150
    4-5 Noise per channel (fC), chip by chip, JTAG=150
    6 Threshold and noise per channel vs chip number, JTAG=150
    7 Average threshold and noise vs chip number, JTAG=150
    8 Threshold and noise residual distributions in fC, (per channel), JTAG=150
    9 Chips with threshold or noise residuals more than 3 sigma , JTAG=150
    10 Threshold and noise per channel, all chips, JTAG=150
    11 Discr. threshold (mV) vs JTAG code
    12-13 Discr. threshold in fC vs threshold in mV, chips 82 and 83
    14-15 Gain (mV/fC) per channel, chip by chip
    16-17 Discr. offset (mV) per channel, chip by chip
    18 Gain and discr. offset distributions
    19 Gain and discr. offset per channel vs chip number
    20 Gain and discr. offset residuals per channel vs chip number
    21 Average gain and discr. offset vs chip number


    Mean time and slewing time distributions are in Fig.2(see also the table below):
    PageHistograms
    1 Mean time, maximum slewing time (for chip and pulser), per channel
    2 Mean time and chip maximum slewing time, per channel vs chip #
    3 Average Mean time and chip maximum slewing time vs chip #
    4 Mean time and chip maximum slewing time per channel, residual
    5 Chips with mean time and max. slewing time to be out of +-3 sigma
    6 Mean time and max. slewing time vs channel #, all chips


    Time resolution at Qin=100 fC, Fig.3 and the table:
    PageHistograms
    1 Time resolution (RMS) per channel and max RMS deviation
    2 Time resolution (RMS) per channel and max RMS deviation vs chip number
    3 Average time resolution (RMS) per channel and max RMS deviation vs chip number
    4 Residuals for time resolution (RMS) per channel and max RMS deviation vs chip number
    5 Chips with residuals of time resolution (RMS) per channel and max RMS deviation more than +- 3 sigma
    6 Time resolution (RMS) vs channel, all chips

  • Summary of results from Pass1.

    • (Mean and Sigma are parameters from the gaussian fit)
    Pass # ParameterMean SigmaComments
    1 Threshold (fC) at JTAG=150 18.3 2.0 Threshold distribution for all channels in all chips, see p. 1 in Fig.1
    - Noise (fC) at JTAG=150 0.95 0.25 Noise distribution for all channels in all chips, see p. 1 in Fig.1
    - Threshold (fC) at JTAG=150, residual - 0.45 Threshold residual distribution for all channels in all chips, see p. 8 in Fig.1. The residual for the given channel was calculated as the difference between the threshold in the channel and the average threshold for given chip.
    - Noise (fC) at JTAG=150, residual - 0.17 Noise residual distribution for all channels in all chips, see p. 8 in Fig.1. The definition of residual is the same as for the threshold.
    - Gain, mv/fC, all channels, all chips 7.9 0.4 See p. 18 in Fig.1.
    - Discriminator offset, mv, all channels, all chips -23 14 See p. 18 in Fig.1.
    - Gain, mv/fC, residual - 0.12 See p. 20 in Fig.1.
    - Discriminator offset, mv, residual - 2.4 See p. 20 in Fig.1.
    - Channel maximum slewing time, nsec
    (Qin = 40 - 800 fC)     		2.8 0.3 See p. 1 in Fig.2.
    - Pulser maximum slewing time, nsec
    (DAC = 500 - 4000)     		0.50 0.14 See p. 1 in Fig.2.
    - Channel mean time residual, nsec
    		- 0.4 See p. 4 in Fig.2.
    - Channel maximum slewing time residual, nsec
    		- 0.2 See p. 4 in Fig.2.
    - Time resolution (RMS), nsec, at Qin=100 fC 0.72 0.09 See p. 1 in Fig.3.
    - Time resolution (RMS), residual, nsec, at Qin=100 fC - 0.08 See p. 4 in Fig.3.

  • Data from the test stand for the chips CMP16B and CMP16C installed on the joint boards AD96D #6,7,8,9 and 10

    • The assignment of the chips to the boards is the following:
    Board #Chips (positions 1-6) Chip submission
    6 09 49 47 33 52 36 CMP16B
    7 78 93 89 99 92 101 CMP16C
    8 84 96 86 91 88 87 CMP16C
    9 94 85 98 77 95 80 CMP16C
    10 31 44 19 51 37 72 CMP16B

    Threshold and noise ( Fig.4 and the table) at JTAG=160 for boards7-9 and JTAG=150 for boards 6,10.
    PageHistograms
    1 Threshold and noise per channel distribution
    2-4 Threshold per channel, chip by chip
    5-7 Noise per channel, chip by chip
    8 Threshold and noise per channel vs chip number
    9 Aver. threshold and noise, JTAG code vs chip number
    10 Aver. threshold and noise, JTAG code distributions
    11 Threshold and noise residuals
    12 Chips with threshold and noise residuals more than +3 sigma
    13 Threshold and noise per channel vs channel number, all chips
    14 Threshold and noise per channel vs chip position on the board, all boards
    15 Threshold and noise per channel vs board number, all chips
    16 Threshold per channel vs channel number of the board, for each board.
    17 JTAG per channel vs channel number of the board, for each board.
    18 Noise per channel vs channel number of the board, for each board.

    Mean time and slewing time distributions are in Fig.5(see also the table below).
    The example for the chip #78 (position 1 on board 7) is here.
    PageHistograms
    1 Mean time, maximum slewing time (for chip and pulser), per channel
    2 Mean time and chip maximum slewing time, per channel vs chip #
    3 Average Mean time and chip maximum slewing time vs chip #
    4 Mean time and chip maximum slewing time per channel, residual
    5 Chips with mean time and max. slewing time to be out of +-3 sigma
    6 Mean time and max. slewing time vs channel #, all chips
    7 Mean time and max. slewing time vs chip position on the board, all boards
    8 Mean time and max. slewing time per channel vs board number, all chips
    9 Mean time vs channel number of the board, for each board.
    10 Max. slewing time vs channel number of the board, for each board.

    teren@fnal.gov bondar@fnal.gov
    Last modified: Fri Jun 25 15:00:00 CST 1999