New version of the amplifier-discriminator chip CMP16

1. 	The chip was submitted to MOSIS using the AMI 1.2 micron technology on 
   November 18, 1998.

   Design name: CMP16 (stands for Carnegie Mellon - Petersburg, 16 channels).

   Description: 16-channel amplifier-discriminator ASIC for the anode signals
                from the muon endcap CSC's.

	The new version of the chip is based on the previous one with an 
attempt to improve its behavior according to the CERN test beam results 
(summer 1998).

2. The beam test results have shown:

  	The anode electronics on the chamber could operate with thresholds
of 40 - 60 fC and they needs significant improvement to work with a
threshold of 20 fC.  Also, the anode amplifier can go into "latch-up"
mode, where all channels on a chip put out a continuous output.
Fortunately, this is not a catastrophe for the chip, but to fix it it
is necessary to switch off the power on the chip and switch it back on 
(this would be a problem for the real set-up).  The anode
amplifier has input noise of 1.0-1.5 fC at Cin=0 pF (the
calculated value was 1.0 fC).  The measured time resolution for the anode
electronics is about right (less than 0.5 nsec for the test signal).

3. Modifications.

3.1 The new iteration of the chip has the same channel structure but
  there are some changes inside the boxes (see the "Front end anode channel 
  structure").

	In the preamplifier (PA), all changes are directed to improve
	the noise behavior and prevent the latch-up mode.  For this:

	- the area of the input transistor was increased by a factor of two;
	- the "current source" of the collector load is replaced by
	  a passive resistor.

	In the shaper stage (Sh.) - the "conveyer" shaper is replaced by 
        an "active R-C" shaper. In this case, the shaping time constant 
        T=R*C is more stable vs. the various transistor parameters and regimes.

	The high threshold enable discriminator (DE) - made very symmetrical.  

	The constant fraction shaper (ShT) - modified to increase the input 
        amplitude range.

3.2	Layout changes:
	
	chip size  - 4.69 x 3.64 mm;
	increased the ground bus width inside the chip;
	increased  the power bus width inside the chip;
	"guard ring" divided into two sections - one each for input
        and output;
	improved isolation between channels;
	improved isolation between analog and digital parts of each channel;
	added filtering capacitors for each channel.
 
3.3  Packaging:

	new package -  Quad Plastic Package (QPP) 14 x 14 mm;
	the chip substrate is connected to the "ground" pins;