A.Golyash
                                                                 Fermilab
                                                             	 Feb. 20, 1999
			  ASIC Test Stand.

1. The goals are to measure for each channel of ASIC at different Cin 
   the thresholds (fC), the slewing time, the gain, the noise and the 
   discriminator level.
   The prototype of the stand was designed and built at PNPI. The second
   prototype now is working at Fermilab.

2. Layout of the stand.

	PC based stand makes use of CAMAC to provide the input test pulse for
   the anode card with 6 ASIC chips on it. It reads out the time from 
   Le Croy 3377 TDC module with 0.5 nsec bin. Other equipment includes:

	- JTAG Byte Blaster to set the threshold of discriminator
	- 4 channel Pulse Generator with calibrated amplitude
	- Input Adapter , 32 channels with sets of input capacitance Cin
	- anode board with 6 chips
        - 32 Channel LVDS/ECL Translator.
	- digital scope

	The software to run the CAMAC, to analyze data on-line and display the
   histograms were written in C++. More advanced analysis of data is made in PAW
   (see www-hep.phys.cmu.edu/cms/AD96a_chip_PNPI_test_98.html for details).

3. Examples of distributions are in file "Figures".

	Pages 1-2 are the threshold curves. The fit was done by Fermi function 
which gives the threshold as the input charge Qin(fC) corresponding to 
efficiency of 50%. The real JTAG was 181 (JTAG in the title is symbolic).
	The threshold and noise for each channel are presented on the page 3. 
The noise was estimated as RMS of the distribution obtained from fitted Fermi 
function by differentiation.