Anode Front-end Electronics current status

 	Our goals were:
        --------------

1. Prepare everything for integration 16 channel Anode Front End
   Board (AFEB) with the chamber and ALCT.

   Problems to study:
	- Pick up noise, Channel to channel cross talk, grounding and
	  shielding issues
	- Connection with ALCT and digital noise cross talk
	- Cathode board to AFEB cross talk
	- Power supply cross talk
	- Test pulsing 

   Hardware problems:
	- AFEB fixation 
	- AFEB grounding solution
	- AFEB shielding solution
	- Signal cable solution
	- Power supply solution

2. Further studying the CMP16-C and CMP8 chip,
   preparation for the "pilot submission".


	What was done:
	-------------

1. Integration.

AFEB behavior on the chamber was studied.
Simple model for pickup noise and additional cross talk was 
proposed  (App.1). According this model we find the best layout for 
cabling and grounding. We have estimated "the ground noise 
current" on the chamber - this value is about 50uA under normal 
condition when everything is quiet - "quiet" condition.
 
 There is a comparison for "good" and "poor" ground 
solution on   Fig.1 and  Fig.2 for "quiet" chamber conditions.

On  Fig.3 and Fig.4  there is a "good" ground effect for cross 
talk between 4 wire groups in one chip (channel 1- 16) under the 
test pulse conditions. The second chip (channels 65 - 80) was let 
without changes for comparison.

Cross talk Cathode to Anode electronics when cathode 
electronics works in the test mode after all modifications was 
pretty small (extra noise less that noise on  Fig.2).

Cross talk from Power supply after Phil's modifications 
became compatible with the noise on  Fig.2.

Cross talk ALCT to AFEB is not studied yet. But most 
measures are proposed. 

Test pulsing problems is under investigations. Currently we 
follow "two test options" way.  It implies that ALCT board will 
have two possibilities to send a test pulse to the chip input and to 
the test strip.  
	We know how to connect AFEB to chamber and "good" 
ground  "in principle" but technical solution for each topic is in 
progress.
 

2. Chips study.

The main problem we have hit in CERN was pretty big cross 
talk. There was a big problem find the reason for this cross talk.
The cross talk in chip CMP8 and in chip CMP16 was measured 
and it value was less than 0.5% inside chip. The most cross talk we 
can receive from a "poor" ground, long input cable and other 
parasitic channel to channel capacitance inside and out the 
chamber.  This problem is still under investigation.


3. Electronics production and planning.

	The new AD16 board was designed and sent for production.
	We hope to receive the "September" submission chips in the 
beginning of December and test them.
	We hope to receive 8 channel delay chip after November 25.
After that we have about 10 days for testing this chip.
We have settled the most questions with this chip performance:
	Slow control interface, signal levels, pin assignment, signal 
levels, and other details. Sent request to company to find  proper 
packaging.

	But we have one very bad news - AMI cancelled 1.2u 
technology and opened 1.5u technology (they assume that this 
technology  stable and  more reliable analog BiCMOS technology).
I recognized this news very recently and did not understand yet the 
scale of this "disaster", but we need redesign all our chips for this 
new technology. This problem is under investigations. In the worst 
case we can slip for two-three months with the pilot submission 
from our "optimistic" schedule. 
So according current understanding the pilot submission may be in 
the beginning of April for CMP16 chip. 
	As to Delay chip the situation is more stable - if we find 
correct package for this chip just now, we will be about in our 
previous schedule.  We will submit this chip in January and get 
back in the beginning of April. And if everything be all right we 
can make a pilot submission for this chip also in April.