Anode electronics current status

1.1 Assignment:

	CMP16_A - first  16 channel chip, was tested in CERN last year
	CMP16_B - November 98 submission, under test now.
	CMP16_C - submitted in March 99. We hope to get it in the end of May.
	CMP8_C  -  8 channels chip option, submitted in March 99

	All chips submitted via MOSIS to AMI BiCMOS1.2u .

1.2 Chip CMP16_C.  (Layout - Fig.1) 

	Schematic of the CMP16_C  chip is about the same like for
CMP16_B, but some items were corrected:

	- Input stage corrected to increase stability with big input 
	  capacitance;
	- Output buffer changed to make it more balanced;
	- Discriminator improved for better performance under big 
	  amplitude of input signals (more than 300fC);
	- Increased ground busses and bypass capacitors in any 
 	  available places;
	- Corrected few small bugs.

1.3 Chip CMP8_C.  (Layout - Fig.2) 

	This is the 8 channels chip. The main idea of the chip is the same 
like in previous iterations, but here the "digital" part of the channel was 
removed to eliminate the digital part of crosstalk:

	- JTAG controlled delay
	- Output pulse width shaper.
	- Also channel to channel isolation was improved.

We hope to receive this chip in the middle of May (because this is 
a standard MOSIS package)

CMP16_B chips was delivered in the end of March.
Package: ASAT-QFP 80pins 0.8mm pitch.

Production statistics:

	received packaged chips		74
	broken chips			2
	tested on bench 		72


Measured parameters :

	Power voltage			3 - 6 V
	Power current			50 - 90 mA
	Input signal range		5fC -  1000fC
	Input noise 			~1 fC  @ Cin = 0 pf
					1.3 fC @ Cin = 180 pF
	Threshold			voltage adjustable 0-100 fC
        Min available threshold 	5 fC  @ Cin=0pF
     					10 fC @ Cin=220pF

Output pulse:

	Output pulse levels		compatible to LVDS
	Output pulse width		current adjustable 30 - 150 ns
	Output pulse delay		3 bits controlled
		Min delay			100ns
		Max delay			130ns
		Step delay			2 - 5 ns (adjustable)

Problems:

 	The chip is not stable enough under nominal power voltage with 
input capacitance Cin > 50 pF. All measurements were performed  with 3.1 V 
applied to the chip.

This board is only analog board. We assume that this is a prototype of the 
combined board and we can use it for test purposes. Five analog boards have 
been made. One was supplied with special sockets to use for testing the chips.
Four other boards will be assembled for testing on the chamber. Also we have 
to assemble a few (5 - 6) more combined boards.

Board specification:

	Number of channels		96
	Power supply voltage    	5.5V min  15V max
	Current				0.4A	  0.6A max
	Input connectors		2x34 pins two row (Condo) x 3
	Output connectors		34 pins two row x 6
	"JTAG" input			10 pins two row
	"JTAG" output			10 pins two row  
	Test pulse 			6 pins two row
	Power  supply			2 pins MOLEX 26-48-1026

Inputs:
	Min detectable signal		10fC @Cin = 180 pF
	Max detectable signal		1000 fC
	Input protection		static voltage protected

Shaping time 				30ns
Input noise				1.0 fC @ Cin = 0 pF
					1.3 fC @ Cin = 220 pF
Threshold setting 
(JTAG" controlled for each chip)	0 - 100 fC
 
Monitoring for each chip 		JTAG readable threshold voltage 

Output pulse:

	Pulse width 		40 -120 ns ("screwdriver" adjustable)
	Delay 			0 - 7 steps ("JTAG" controlled)
	Delay step 		"screwdriver" adjustable   1 - 5 ns
	Slewing time 		2ns

Test pulse:				

	Test pulse trigger	external pulse (LVDS levels)
	Test pulse amplitude	8 bit DAC on board (JTAG controllable)
	Each chip may be fired 
	separately

On board monitoring:
	 	 
	On board temperature
	Consuming current
	"JTAG" 	LVDS levels (non standard)

One AD96_B board is assembled, tuned and tested (Fig.3)

Indeed there are three stands in one setup:

	-stand for studying chip performance
	-stand for testing and separating chips
	-stand for tuning and testing anode board 

It is possible to say that stand #1 is ready. There is setup for 2 chips and 
few programs. With this stand we have tested two old (CMP16_A) chips and one 
very first new chip (CMP16_B). All standard parameters (gain, noise, threshold,
slewing time, delay) were measured. 

	 Fig.4  - For the chip CMP16_B at Cin = 220 pF we have studied cross 
talk behavior vs number of incorporated channels. Digital part of crosstalk 
is in 3 times bigger than analog one. Stable threshold is 30 - 40 fC at
Cin = 220 pF. There are two ways to improve this situation : minimize input 
capacitance, minimize internal digital crosstalk. 

	 Fig.5  - Comparison of old chips CMP16A and new chip CMP16B stability 
at Cin = 220 pF 

Stand number 2 is not ready. Actually we used the same setup for testing first
74 chips and part of the same programs. It is not convenient and we are 
planning to design special adapter for connecting chips and modify existing 
programs for this application. Also we need understand the best way for fast 
and effective method of separation the chips. Any way we have tested all 
74 and there are first results:

	 Fig.6  - Threshold and noise statistic
	 Fig.7  - Propagation and slewing time statistic. No tuning was done 
in the first pass therefore the slewing time is large.
	
Stand number 3 is not ready also. We have all necessary equipment, but we 
need modify our programs for 96 channels. 
 
So our first board AD96_B was tuned and tested with the Stand#1.

On bench test results:
		
	Min. achieved threshold 	  12 fC 	@ Cin = 180 pF  
	Slewing time			< 1.5 ns  	@ Qin = 50 - 900 fC

	 Fig.8  - Threshold and noise board performance 
	(Ad96_B board #1 parameters after tuning).
	 Fig.9a  Fig.9b  - Slewing time curves for two typical chips #4 and #2 
	(Ad96_B board #1 parameters after tuning). 
	 Fig.10  - Propagation and slewing time board performance 
	(Ad96_B board #1 parameters after tuning).

Anode board #1 was assembled and tuned and tested on bench. After that we 
have tested this board on chamber PC2. This board was connected to the wide 
side of the chamber and tested with test pulses.

 - Board #1 on chamber test results:

	Min. available threshold 			23 fC  
	(board on the top of the chamber, Fig.11a )
	Min. available threshold			12 fC 
 	(board attached to the side of the 
	chamber with short cables, Fig.11b ) 

First run on the cosmic muons stand was made. Bunch crossing identification 
efficiency > 92% in 20 ns gate @ HV = 4.0 kV.

How to improve anode electronics behavior? As shown the anode electronics 
peformance  much better when amplifier connected with very short cable.

There are two possibilities:

	- 48 channels board placed on the side with short input cables
	- 16 channels direct plug-in board  Fig.12