Anode Front End Electronics current status

(presented by N. Bondar, PNPI/CMU)
EMU meeting at the University of Florida, Feb. 18-19, 2000


        - CMP16_D and CMP16_E chip bench test results
        - AD16 board
        - CMP16_F chip status
        - Del_16 delay chip status
        - Anode front-end electronics integration issues
        - Planning for radiation tests

1. CMP16_D and CMP16_E chip bench test result.

The CMP16_D and CMP16_E designs were submitted in September to AMI with the 1.2 micron
technology via MOSIS. Indeed, CMP16_E chip is the same as the  CMP16_D, except the delay
circuit was removed. The reason for these two submissions is to compare the chip with
and without the delay inside the chip.Also, a few small changes were added in the scheme
of the chip to improve channel-to-channel isolation and to remove unnecessary external
bias voltages.

        Results of  "on  bench" measurements are presented in the next table:


Parameters                              CMP16_D                 CMP16_E

Amplifier gain *)                       9 mV/fC                  9 mV/fC

Equivalent input noise @Cin=0 pF        0.6 fC                   0.6 fC
                       @Cin=200pF       1.5 fC                   1.5 fC

Minim. available thr   @Cin = 200pF     20 fC                    20 fC

Threshold control range                 0 fC  - 100 fC           0 fC- 100 fC

Delay:  minimum                         95 ns                    85 ns
        maximum                         125 ns  controllable     87 ns

Slewing time **)                        3 ns                     3 ns

Output pulse width                      20 ns - 150 ns           "width over threshold"
Internal Cross-talk ***)
(worst case)                            1.5% anal.+2.5 fC dig.   1.5%anal.+0.2 fC dig.


*) amplifier gain	**) slewing time	***) crosstalk(at Qin = 100 fC)


        Both of them, CMP16_D and CMP16_E, have almost the same characteristics, but 
chip CMP16_E has:

        less internal delay by 10 ns,
        less internal cross-talk from the "digital" part of 0.2 fC compared to 2.5 fC.

       	One more detail - there are only 3 broken chips out of 14 for CMP16_E, 
but - 6 broken chips out of 14 for CMP16_D. It is obvious that the CMP16_E chip is 
significantly better than the previous samples.

2. AD16 board

        - Introduction.

	The AD16 board is a 16-channel amplifier-discriminator board for the anode 
read-out of the Cathode Strip Chamber (CSC) (see  ad16_p2_1.gif)). This board is 
designed for direct connection to the chamber. The board has a 34-pin input connector 
and 40-pin output connector. During standard working conditions, this board is connected
to the ALCT board with a 20 twisted-pair cable. This cable is used both to transmit 
output signals to the ALCT and to supply the board with power voltage, threshold voltage
and test pulsing. All these voltages are produced by the ALCT device. For testing the 
anode electronics with TDC's, a special LVDS/ECL converter module will be designed. 
This converter will receive LVDS signal and transmit them in ECL standard to the TDC. 
Also, the module will supply the  AD16 board with power and threshold voltages.
Threshold voltage must have the possibility of manual adjustment and easy monitoring.

        - AD16 board specification:

Board dimensions                2.8" x 3.075" x 0.625"
Input connector                 strip socket,  two row, 34 contacts
Output connector                40-pin header.
Inputs                          DC isolated
Output                          current source LVDS compatible
Power supply voltage            +5.5 V
        minimum                 +4 V
        maximum                 +6 V
Current                         0.1 A @+5.5 V
Threshold voltage               0 - 1.7 V control range
                                0 - maximum threshold
Test pulse:
        termination             110 Ohm
        pulse-charging          0.25 mV/fC
        max. amplitude          2V

       - Safety features:

	Wrong connection of the AD16 board with the chamber does not damage either the 
board or the protection board. Wrong polarity of  the output cable will not damage the 
AD16 board if all signals and voltages are within standard levels.

        Assembling drawing and actual size of the board is AD16_assembl.gif.

        Input and Output connector specification is in a circuit diagram of the board  
- ad16_p1_1.gif.

        - Production conditions:

 	The AD16 board will be assembled, debugged and tested during the production 
flow. Each board must have a label with the item number. The minimum necessary parameters
for the production flow measurement will be extracted. Results of the measurements will 
be placed in a database.

3. CMP16_F chip status

        At the very end of 1999, the MOSIS changed their design rules for BiCMOS AMI 
technology from 1.2 to 1.5 microns, according AMI recommendation. This change was made to
improve the stability of the process parameters. So we had to change the layout of the 
CMP16_E to suit these new rules. The new chip is named CMP16_F. Simplified schematic of 
this chip is presented   here.The full set of schemes for this design is also available.
The actual die size of the chip is a little bit bigger that the previous one, but it 
still fits in the same package (QFP 80). The chip layout is presented

       The CMP16_F chip was submitted to MOSIS  on January 15, 2000 and will be back in
March  (according to the MOSIS schedule). 90 chips were ordered. That is enough to equip
3 chambers and have some number of chips left  to test with a proton beam. If the result 
of this submission will be perfect, we will  ready for mass production, after the 
radiation hardness test.

4. Del_16 delay chip status

	The 16-channel delay chip was designed to provide a compact LVDS to CMOS level 
converter and a controllable delay circuit for anode signals. Since the anode pulse 
arriving time must be aligned with an of accuracy 2-3 ns, this delay circuit does not 
have to be very precise, but must be low power consuming and easily controlled.
Schematic of this circuit was tested in a previous submission to AMI1.2 microns technology
via MOSIS. The chip name is DEL8. This chip was tested and results were pretty good.
The delay channel structure is presented here.
	A serial interface was implemented in this chip to control delay. This interface
consists of a four-bit shift register. It is possible to connect these shift registers 
in a daisy chain. Interface schematic presented in  shift_reg_1.gif.
	The new chip was designed for AMI 0.5 micron. Layout of this chip - here.

        Chip specification (calculated figures)

Chip delay, minimum             - 20 ns
            maximum             - 52 ns
Delay step                      -  2 ns  (adjustable "on board" by setting 
					 "Pulse delay" current (Id))
Delay steps                     - 15
Delay code                      - 4 bit
Output pulse width              - 20 ns - 100 ns (adjustable "on board" by setting
                                                 "Pulse width" current (Iw))
Control interface signals       - Reset (CLRB)- set all registers to zero, minimum delay.
                                - Chip select bar (CHSB) select chip to download data
                                - Clock (CLK)
                                - Data Input (DIN)
                                - Data Out   (DOUT)

        Chip submitted to MOSIS for production January 21 and will be back March 30
(according the teh MOSIS schedule). As far as delay chip will be ready only in April,
to supply ALCT board testing with real pulses a special LVDS/TTL adapter was designed

5. Anode front-end electronics integration issues

        - Board fixation

Each AD16 board is directly connected to a protection board on the chamber. Special slots
are made in the anode side cover of the chamber. The size of the slot is fixed. Two holes
for the "grounding" screws will be drilled near each slot. A special cover box has been 
designed for the boards. This box will mechanically protect the boards, support the 
boards and make electrical  shield for the boards. So this board must be strong and well
connected to the chamber cover. The construction of the box and the slots and the other 
holes on chamber was discussed and a solution was agreed. To insure that everything is 
okay, a simple mock-up will be made at Fermilab. We think that the latches on the 
protection board connector are not needed.

        - AD16 ALCT cabling

We assume that every cable may have its own length. But in reality it will be a set of
cables with a few lengths. Every cable must have a strain relief on the AD16 side, as
well as on  the ALCT side. There is a proposal for these devices. How cables must be 
arranged on the top of the chambers is still under discussion.

        - AD16 boards cooling

I am pretty sure that for the most chambers we do not need special cooling system for
the anode front-end electronics. But there are a few places where the AD16 boards are
located pretty close. We are planning to perform special temperature measurement to get
an answer for cooling these places.

6. Radiation test.

     One effect of radiation is to cause Single Event Upset (SEU) in a chip, such as it
doing into latch-up mode. We need to measure the probability of this happening with our
amplifier chip as a function of the radiation dose. We will join the rest of the endcap
muon electronics groups in this effort to measure the effect of radiation.
The AD16 board is very well suited for this test. There is only one chip on this board.
The power regulator on the board can be disabled, or even tested separately.We would 
like to discuss and prepare all the special equipment needed for monitoring the power 

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Last modified: Apr 03 09:00:00 CST 2000