- The example of the time distributions of the delay chip output pulses at
maximum delay code of 15 is given in
Time (*.ps),
Time (*.gif) and corresponding mean time
- in
Mean time (*.ps),
Mean time (*.gif). The max and min widths
of the time distributions at the base for each chip from the first set are in
Width (*.ps),
Width (*.gif). For the 1000 input
test pulses sample 1 ns < width < 2 ns and more than 80% of pulses is within
the window of 1 ns (see the bottom graph in
Width (*.ps),
Width (*.gif)).
No inefficiency was observed in the sample of data with 1000 input pulses
(the first set).
- The maximum difference in delays between channels within the chip for each
delay code is given in
Fig.1 (*.ps),
(*.gif), chip by chip. Five chips
(## 21,22,24,38 and 147) show the
difference of more than 3 nsec. See also summary on the first graph in
Fig.2 (*.ps),
(*.gif)
- The delay time vs delay code dependence was fitted by the straight line
for each channel in all chips with offset and slope as free parameters (see
example in
Fit (*.ps),
(*.gif)).
The maximum differential non-linearity defined
as the largest absolute residual within the given chip is presented in graph 2
of Fig.2 (*.ps),
(*.gif) for each chip. The residuals
were defined as the difference between data and fit.
The residuals averaged over all channels in all 157 chips are plotted in
Aver. residual (*.ps),
(*.gif) vs delay code. Four groups
of delays provided by combinations of four capacitances are clearly seen.
The residual at the delay code of 8 is almost -0.5 ns.
The offsets (as delay time at delay code = 0)
and the slopes are given in
Fig.3 (*.ps),
(*.gif). The average,
min. and max. values of these parameters per chip are plotted. The offsets
include the apparatus delay (we have to measure it and subtract from the future
data to get the intrinsic initial delay of the chips). The apparatus delays
in both sets were different. For the second set of data (chips 26-158) it was
about 70 ns.
- The maximum and minimum differential slopes (change of delay per delay code)
are given in
Fig.4 (*.ps),
(*.gif)
There are about 30% of chips with minimum differential slope less than 1 ns.
Note that the fitted slopes are
sitting in the region of 2.4 - 2.7 nsec (
Fig.3 (*.ps),
(*.gif)). Almost all minimum
slopes occur ar delay code of 8 (the bottom graph in
Fig.4 (*.ps),
(*.gif)).
For this code the delay in each channel is provided by one largest capacitance
while for all others - by combination of capacitances.
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Introduction.
